1. Field of the Invention
The present invention relates to transistor of semiconductor device and method for manufacturing the same, and in particular to an improved transistor of semiconductor device and a method for manufacturing the same wherein only one voltage generation and control circuit is required and formation of a source/drain region by self-align method is possible to reduce the cell and the chip areas and improve the yield and reliability of the device.
2. Description of the Background Art
A conventional Electrically Erasable Programmable Read Only Memory (“EEPROM”) type floating gate flash memory employs a memory cell comprising a vertical stack of tunneling oxides, a first polysilicon layer disposed on the tunneling oxides, an oxide-nitride-oxide (“ONO”) interlayer dielectric disposed on the first polysilicon layer and a second polysilicon layer disposed on the ONO interlayer dielectric.
Generally, a flash memory cell is programmed by inducing a hot electron injection from a portion of substrate such as a channel region, which is adjacent to a drain region, into floating gate. Negative charges are carried into the floating gate by the injection of electrons. Specifically, a source region and a bulk substrate are connected to ground, a relatively high positive voltage is applied to a control electrode to induce an electrical field, and a certain amount of positive voltage is applied to the drain region to generate “hot” (high energy) electron in order to induce the hot electron injection. The negative potential of the floating gate increases the threshold voltage and suppresses the current flow through the channel region during a subsequent read mode after a sufficient amount of negative charges is accumulated in the floating gate. The read current determines the programming of the flash memory cell. A discharge function of the floating gate of the flash memory cell is called an erase operation. Typically, the erase operation is performed by Fowler-Nordheim tunneling mechanism between the floating gate and the source region of a transistor (source-erase or negative gate-erase) or between the floating gate and the substrate (channel-erase). The source-erase operation is induced by applying a high voltage to the source region and a voltage of 0V to the control gate and to the substrate and by simultaneously floating the drain of each memory cell.
A silicon-oxide-nitride-oxide-silicon (“SONOS”) type memory device has been introduced. A SONOS type flash memory cell electron typically comprises charge trapping non-conductive dielectric, i.e. two silicon oxide layers having a silicon nitride layer (insulation layer) therebetween. The non-conductive dielectric serves as an electrical electron-trapping medium. A conductive gate layer is disposed on the upper silicon oxide layer. Because the electrical charges are trapped in a portion adjacent to a drain region, this structure is a 2-transistor cell, i.e. two bits can be stored per cell. When multiple levels are used, four or more bits can be stored per cell. A multiple bit cell has advantages over other devices in that SONOS type memory device increases amount of information stored/processed in an integrated circuit.
FIG. 1 is a cross-sectional diagram illustrating a conventional transistor.
Referring to FIG. 1, a conventional SONOS cell transistor comprises a gate oxide film 12 disposed on a semiconductor substrate 10, a word line gate electrode 14 disposed thereon, an interlayer dielectric 26 including a stacked structure of an oxide film 16, an nitride film 18 and an oxide film 20 disposed on a side wall of word line gate electrode 14 and the semiconductor substrate 10 at both sides of word line gate electrode 14, a control gate electrode 22 disposed on the interlayer dielectric 26, and source/drain regions 24 disposed on an active region of semiconductor substrate 10 at both sides of the control gate 22.
The transistor has a structure including three transistors of a control transistor, word line transistor and another control transistor connected in series between source/drain regions. The threshold voltage of the control transistor is varied by the electrons trapped in the oxide-nitride-oxide (“ONO”) insulating film under the control gate. Therefore, if in case that there are electrons in each ONO gate insulating film is designated as ‘0’ (or ‘1’) and in case that there are no electrons as ‘0’ (or ‘1’), the above transistor structure is a 2 bit cell transistor which can store two ‘0’s and ‘1’s.
Table 1 below shows operation of the conventional transistor.
TABLE 1Word linegateControl gateDrain/sourceReadSelect1.8 V  1.8 V and >2.8 V1.5 V and 0 VUnselect0 V1.8 V  1.8 VProgramSelect1.0 V  5.5 V and >2.8 V4.5 V or 0 VUnselect0 V1.8 V  1.8 VEraseSelect0 or floating−3 V  4.5 VUnselect0 V1.8 V or 0 V
Referring to Table 1, it should be noted that program operation requires high voltages applied to the control gate and the drain/source region.
In accordance with the conventional transistor, three transistors including two control transistors and a word line transistor are used to store 2 bits of data and different voltages are applied to the control gate and the word line gate. Therefore, a voltage generation and control circuit for the control gate as well as a voltage generation and control circuit for the word line gate is required, resulting in an increase of chip area.
In addition, because the control gate is formed on the sidewall of the word line gate, a contact plug of the source/drain regions is not self-aligned. Therefore, the contact plug and the control gate must be spaced apart form each other to prevent short therebetween due to misalignment, resulting in an increase of cell area.